1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2010-248769, filed Nov. 5, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, with the development of miniaturization of semiconductor devices such as DRAMs, Dynamic Random Access Memories, specifically, miniaturization of semiconductor elements, it is becoming difficult to form a miniaturized island-shaped active region, element forming region surrounded by an element isolation region, STI (shallow trench isolation) region in a semiconductor substrate using photolithography and dry etching.
For a DRAM, a buried gate electrode, a pair of impurity diffusion regions, source/drain regions, and the like constituting a selection transistor are formed in the active region, element forming region.
When the miniaturized island-shaped active region is formed using the photolithography and the dry etching, the photolithography and the dry etching may not be well performed. Accordingly, both ends of the active region are rounded and an area of an upper surface of the active region becomes smaller than a desired value.
If an impurity diffusion region is formed in an end of the active region having such a shape, an area of an upper surface of the impurity active region becomes smaller than a desired value.
Accordingly, since an area of a contact between a contact plug contacting the upper surface of the impurity diffusion region and the impurity diffusion region also becomes small, contact resistance between the impurity diffusion region and the contact plug becomes great.
As a means for resolving such problems, a device including an element isolation region (STI region) consisting of an insulating film burying a trench formed in a semiconductor substrate and partitioning an active region extending in a first direction, and a dummy gate electrode arranged through an insulating film in a dummy gate trench (a trench formed in the semiconductor substrate) extending in a second direction intersecting the first direction and functioning as an element isolation region that partitions the active region into a plurality of element forming regions when a reverse bias is applied is disclosed in Japanese Patent Laid-open Publication No. 2010-141107.
Since the reverse bias is applied to cause the dummy gate electrode to function as an element isolation region, on current of an adjacent selection transistor cannot be sufficiently secured or junction leak current increases due to the reverse bias. Accordingly, a data retention characteristic of a DRAM is degraded.